MC9S12XD256MAL Datasheet, PDF (1265/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Appendix A Electrical Characteristics
A.5 Reset, Oscillator, and PLL
This section summarizes the electrical characteristics of the various startup scenarios for oscillator and
phase-locked loop (PLL).
A.5.1 Startup
Table A-21 summarizes several startup characteristics explained in this section. Detailed description of the
startup behavior can be found in the Clock and Reset Generator (CRG) Block Guide.
Table A-21. Startup Characteristics
Conditions are shown in Table A-4unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
1 D Reset input pulse width, minimum input time
2 D Startup from reset
3 D Interrupt pulse width, IRQ edge-sensitive mode
4 D Wait recovery startup time
5 D Fast wakeup from STOP²
1 _{1 tcycle at 40Mhz Bus Clock}
2 _{VDD1/VDD2 filter capacitors 220 nF, VDD35 = 5 V, T= 25°C}
PW_RSTL
2
—
—
t_osc
n_RST
192
—
196
n_osc
PW_IRQ
25¹
—
—
ns
t_WRS
—
—
14
t_cyc
t_fws
—
50
—
µs
A.5.1.1 POR
The release level V_PORR and the assert level V_PORA are derived from the V_DD supply. They are also valid
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time t_CQOUT no valid oscillation is detected, the MCU will start using the internal self
clock. The fastest startup time possible is given by n_uposc.
A.5.1.2 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when V_DD35 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG flags register has not been set.
A.5.1.3 External Reset
When external reset is asserted for a time greater than PW_RSTL the CRG module generates an internal
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
A.5.1.4 Stop Recovery
Out of stop the controller can be woken up by an external interrupt. A clock quality check as after POR is
performed before releasing the clocks to the system.
Freescale Semiconductor
MC9S12XDP512 Data Sheet, Rev. 2.21
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