MC9S12XD256MAL Datasheet, PDF (873/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2.64 Port AD0 Reduced Drive Register 1 (RDR1AD0)
7
R
RDR1AD07
W
6
RDR1AD06
5
RDR1AD05
4
RDR1AD04
3
RDR1AD03
2
RDR1AD02
1
RDR1AD01
0
RDR1AD00
Reset
0
0
0
0
0
0
0
0
Figure 22-66. Port AD0 Reduced Drive Register 1 (RDR1AD0)
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each output pin PAD[07:00] as either full or reduced. If the
port is used as input this bit is ignored.
Table 22-59. RDR1AD0 Field Descriptions
Field
Description
7–0
Reduced Drive Port AD0 Register 1
RDR1AD0[7:0] 0 Full drive strength at output.
1 Associated pin drives at about 1/6 of the full drive strength.
22.3.2.65 Port AD0 Pull Up Enable Register 1 (PER1AD0)
7
R
PER1AD07
W
6
PER1AD06
5
PER1AD05
4
PER1AD04
3
PER1AD03
2
PER1AD02
1
PER1AD01
0
PER1AD00
Reset
0
0
0
0
0
0
0
0
Figure 22-67. Port AD0 Pull Up Enable Register 1 (PER1AD0)
Read: Anytime.
Write: Anytime.
This register activates a pull-up device on the respective pin PAD[07:00] if the port is used as input. This
bit has no effect if the port is used as output. Out of reset no pull device is enabled.
Table 22-60. PER1AD0 Field Descriptions
Field
7–0
Pull Device Enable Port AD0 Register 1
PER1AD0[7:0] 0 Pull-up device is disabled.
1 Pull-up device is enabled.
Description
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
875