MC9S12XD256MAL Datasheet, PDF (791/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 21 External Bus Interface (S12XEBIV2)
21.3.2.2 External Bus Interface Control Register 1 (EBICTL1)
R
W
Reset
7
EWAITE
0
6
5
4
3
2
1
0
0
0
0
EXSTR2 EXSTR1
0
0
0
0
1
1
= Unimplemented or Reserved
Figure 21-4. External Bus Interface Control Register 1 (EBICTL1)
0
EXSTR0
1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data are read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
This register is used to configure the external access stretch (wait) function.
Table 21-5. EBICTL1 Field Descriptions
Field
Description
7
EWAITE
External Wait Enable — This bit enables the external access stretch function using the external EWAIT input
pin. Enabling this feature may have effect on the minimum number of additional stretch cycles (refer to
Table 21-6).
External wait feature is only active if enabled in normal expanded mode and emulation expanded mode; function
not available in all other operating modes.
0 External wait is disabled
1 External wait is enabled
2–0
EXSTR[2:0]
External Access Stretch Bits 2, 1, 0 — This three bit field determines the amount of additional clock stretch
cycles on every access to the external address space as shown in Table 21-6. The minimum number of stretch
cycles depends on the EWAITE setting.
Stretch cycles are added as programmed in normal expanded mode and emulation expanded mode; function
not available in all other operating modes.
Table 21-6. External Access Stretch Bit Definition
EXSTR[2:0]
000
001
010
011
100
101
110
111
Number of Stretch Cycles
EWAITE = 0
1 cycle
2 cycles
3 cycles
4 cycles
5 cycles
6 cycles
7 cycles
8 cycles
EWAITE = 1
>= 2 cycles
>= 2 cycles
>= 3 cycles
>= 4 cycles
>= 5 cycles
>= 6 cycles
>= 7 cycles
>= 8 cycles
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
793