MC9S12XD256MAL Datasheet, PDF (70/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 1 Device Overview MC9S12XD-Family
Table 1-9. Chip Modes and Data Sources
Chip Modes
BKGD =
MODC
PE6 =
MODB
PE5 =
MODA
PK7 =
ROMCTL
PE3 =
EROMCTL
Data Source¹
Normal single chip
1
0
0
X
X
Internal
Special single chip
0
0
0
Emulation single chip
0
0
1
X
0
Emulation memory
X
1
Internal Flash
Normal expanded
1
0
1
0
X
External application
1
X
Internal Flash
Emulation expanded
0
1
1
0
X
External application
1
0
Emulation memory
1
1
Internal Flash
Special test
0
1
0
0
X
External application
1
X
Internal Flash
1 _{Internal means resources inside the MCU are read/written.}
Internal Flash means Flash resources inside the MCU are read/written.
Emulation memory means resources inside the emulator are read/written (PRU registers, Flash replacement, RAM, EEPROM,
and register space are always considered internal).
External application means resources residing outside the MCU are read/written.
The configuration of the oscillator can be selected using the XCLKS signal (see Table 1-10). For a detailed
description please refer to the S12CRG section.
Table 1-10. Clock Selection Based on PE7
PE7 = XCLKS
Description
0
Full swing Pierce oscillator or external clock source selected
1
Loop controlled Pierce oscillator selected
The logic level on the voltage regulator enable pin V_REGEN determines whether the on-chip voltage
regulator is enabled or disabled (see Table 1-11).
Table 1-11. Voltage Regulator VREGEN
V_REGEN
1
0
Description
Internal voltage regulator enabled
Internal voltage regulator disabled, V_DD1,2 and V_DDPLL must be
supplied externally
MC9S12XDP512 Data Sheet, Rev. 2.21
70
Freescale Semiconductor