MC9S12XD256MAL Datasheet, PDF (454/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
Module Base + 0x0004 (DSR0)
0x0005 (DSR1)
0x0006 (DSR2)
0x0007 (DSR3)
0x0008 (DSR4)
0x0009 (DSR5)
0x000A (DSR6)
0x000B (DSR7)
7
R
DB7
W
6
DB6
5
DB5
4
DB4
3
DB3
2
DB2
1
DB1
0
DB0
Reset:
x
x
x
x
x
x
x
x
Figure 10-34. Data Segment Registers (DSR0–DSR7) — Extended Identifier Mapping
Table 10-31. DSR0–DSR7 Register Field Descriptions
Field
7:0
DB[7:0]
Data bits 7:0
Description
10.3.3.3 Data Length Register (DLR)
This register keeps the data length field of the CAN frame.
R
W
Reset:
7
6
5
4
3
2
1
DLC3
DLC2
DLC1
x
x
x
x
x
x
x
= Unused; always read “x”
Figure 10-35. Data Length Register (DLR) — Extended Identifier Mapping
0
DLC0
x
Table 10-32. DLR Register Field Descriptions
Field
Description
3:0
DLC[3:0]
Data Length Code Bits — The data length code contains the number of bytes (data byte count) of the respective
message. During the transmission of a remote frame, the data length code is transmitted as programmed while
the number of transmitted data bytes is always 0. The data byte count ranges from 0 to 8 for a data frame.
Table 10-33 shows the effect of setting the DLC bits.
MC9S12XDP512 Data Sheet, Rev. 2.21
454
Freescale Semiconductor