MC9S12XD256MAL Datasheet, PDF (831/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2.10 Port E Data Direction Register (DDRE)
7
6
5
4
3
2
1
0
R
0
0
DDRE7
DDRE6
DDRE5
DDRE4
DDRE3
DDRE2
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 22-12. Port E Data Direction Register (DDRE)
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data are read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Table 22-13. DDRE Field Descriptions
Field
Description
7–0
DDRE[7:2]
Data Direction Port E — his register controls the data direction for port E. When Port E is operating as a general
purpose I/O port, DDRE determines whether each pin is an input or output. A logic level “1” causes the
associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input.
Port E bit 1 (associated with IRQ) and bit 0 (associated with XIRQ) cannot be configured as outputs. Port E, bits
1 and 0, can be read regardless of whether the alternate interrupt function is enabled.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PORTE after changing the DDRE register.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
833