MC9S12XD256MAL Datasheet, PDF (713/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

TAGHITS
EXTERNAL TAGHI / TAGLO
XGATE S/W BREAKPOINT REQUEST
SECURE
CPU BUS
XGATE BUS
COMPARATOR A
COMPARATOR B
COMPARATOR C
COMPARATOR D
Chapter 19 S12X Debug (S12XDBGV2) Module
TAGS
BREAKPOINT REQUESTS
CPU & XGATE
MATCH0
MATCH1
MATCH2
MATCH3
TAG & TRIGGER
TRIGGER
CONTROL
LOGIC
STATE
STATE
SEQUENCER
TRACE
CONTROL
TRIGGER
READ TRACE DATA (DBG READ DATA BUS)
TRACE
BUFFER
Figure 19-22. DBG Overview
19.4.2 Comparator Modes
The DBG contains 4 comparators, A, B, C, and D. Each comparator can be configured to monitor either
CPU or XGATE busses using the SRC bit in the corresponding comparator control register. Each
comparator compares the selected address bus with the address stored in DBGXAH, DBGXAM and
DBGXAL. Furthermore comparators A and C also compare the data buses to the data stored in DBGXDH,
DBGXDL and allow masking of individual data bus bits.
All comparators are disabled in BDM and during BDM accesses.
The comparator match control logic (see Figure 19-22) configures comparators to monitor the busses for
an exact address or an address range, whereby either an access inside or outside the specified range
generates a match condition. The comparator configuration is controlled by the control register contents
and the range control by the DBGC2 contents.
On a match a trigger can initiate a transition to another state sequencer state (see Section 19.4.3, “Trigger
Modes”). The comparator control register also allows the type of access to be included in the comparison
through the use of the RWE,RW,SZE and SZ bits. The RWE bit controls whether read or write comparison
is enabled for the associated comparator and the RW bit selects either a read or write access for a valid
match. Similarly the SZE and SZ bits allows the size of access (word or byte) to be considered in the
compare. Only comparators B and D feature SZE and SZ.
The TAG bit in each comparator control register is used to determine the triggering condition. By setting
TAG, the comparator will qualify a match with the output of opcode tracking logic and a trigger occurs
before the tagged instruction executes (tagged-type trigger). Whilst tagging the RW, RWE, SZE and SZ
bits are ignored and the comparator register must be loaded with the exact opcode address.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
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