MC9S12XD256MAL Datasheet, PDF (902/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
External Signal Description
This section lists and describes the signals that do connect off-chip.
23.0.3 Signal Properties
Table 23-1 shows all the pins and their functions that are controlled by the PIM. Refer to Section ,
“Functional Description” for the availability of the individual pins in the different package options.
NOTE
If there is more than one function associated with a pin, the priority is
indicated by the position in the table from top (highest priority) to bottom
(lowest priority).
Table 23-1. Pin Functions and Priorities (Sheet 1 of 7)
Port
—
A
B
C
D
Pin Name
BKGD
PA[7:0]
PB[7:1]
PB[0]
PC[7:0]
Pin Function
and Priority
MODC¹
BKGD
ADDR[15:8]
mux
IVD[15:8]²
GPIO
ADDR[7:1]
mux
IVD[7:1]²
GPIO
ADDR[0]
mux
IVD0²
UDS
GPIO
DATA[15:8]
PD[7:0]
GPIO
DATA[7:0]
GPIO
I/O
Description
I MODC input during RESET
I/O S12X_BDM communication pin
O High-order external bus address output
(multiplexed with IVIS data)
I/O General-purpose I/O
O Low-order external bus address output
(multiplexed with IVIS data)
I/O General-purpose I/O
O Low-order external bus address output
(multiplexed with IVIS data)
O Upper data strobe
I/O General-purpose I/O
I/O High-order bidirectional data input/output
Configurable for reduced input threshold
I/O General-purpose I/O
I/O Low-order bidirectional data input/output
Configurable for reduced input threshold
I/O General-purpose I/O
Pin Function
after Reset
BKGD
Mode
dependent³
Mode
dependent³
Mode
dependent³
Mode
dependent³
MC9S12XDP512 Data Sheet, Rev. 2.21
904
Freescale Semiconductor