MC9S12XD256MAL Datasheet, PDF (481/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 11 Serial Communication Interface (S12SCIV5)
11.3.2 Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Writes to a reserved register locations do not have any effect
and reads of these locations return a zero. Details of register bit and field function follow the register
diagrams, in bit order.
Register
Name
Bit 7
SCIBDH¹ R
IREN
W
6
TNP1
SCIBDL¹ R
SBR7
W
SBR6
SCICR1¹
R
LOOPS
W
SCISWAI
SCIASR1² R
0
RXEDGIF
W
SCIACR1² R
0
RXEDGIE
W
SCIACR2² R
0
0
W
5
TNP0
SBR5
RSRC
0
0
0
4
SBR12
SBR4
M
0
0
0
3
2
SBR11
SBR10
1
SBR9
Bit 0
SBR8
SBR3
SBR2
SBR1
SBR0
WAKE
ILT
PE
PT
0
BERRV BERRIF BKDIF
0
0
BERRIE BKDIE
0
BERRM1 BERRM0 BKDFE
SCICR2 R
TIE
TCIE
RIE
ILIE
TE
W
SCISR1 R TDRE
TC
RDRF
IDLE
OR
W
RE
RWU
SBK
NF
FE
PF
SCISR2 R
0
AMAP
W
0
RAF
TXPOL
RXPOL
BRK13
TXDIR
SCIDRH R R8
0
0
0
0
0
0
T8
W
SCIDRL R R7
R6
R5
R4
R3
R2
R1
R0
W
T7
T6
T5
T4
T3
T2
T1
T0
1.These registers are accessible if the AMAP bit in the SCISR2 register is set to zero.
2,These registers are accessible if the AMAP bit in the SCISR2 register is set to one.
= Unimplemented or Reserved
Figure 11-2. SCI Register Summary
1 _{Those registers are accessible if the AMAP bit in the SCISR2 register is set to zero}
2 _{Those registers are accessible if the AMAP bit in the SCISR2 register is set to one}
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
481