MC9S12XD256MAL Datasheet, PDF (844/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2.26 Port S Reduced Drive Register (RDRS)
R
W
Reset
7
RDRS7
0
6
RDRS6
5
RDRS5
4
RDRS4
3
RDRS3
2
RDRS2
0
0
0
0
0
Figure 22-28. Port S Reduced Drive Register (RDRS)
1
RDRS1
0
0
RDRS0
0
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each port S output pin as either full or reduced. If the port is
used as input this bit is ignored.
Table 22-28. RDRS Field Descriptions
Field
Description
7–0
Reduced Drive Port S
RDRS[7:0] 0 Full drive strength at output.
1 Associated pin drives at about 1/6 of the full drive strength.
22.3.2.27 Port S Pull Device Enable Register (PERS)
R
W
Reset
7
PERS7
1
6
PERS6
5
PERS5
4
PERS4
3
PERS3
2
PERS2
1
PERS1
1
1
1
1
1
1
Figure 22-29. Port S Pull Device Enable Register (PERS)
0
PERS0
1
Read: Anytime.
Write: Anytime.
This register configures whether a pull-up or a pull-down device is activated, if the port is used as input or
as output in wired-OR (open drain) mode. This bit has no effect if the port is used as push-pull output. Out
of reset a pull-up device is enabled.
Table 22-29. PERS Field Descriptions
Field
Description
7–0
Pull Device Enable Port S
PERS[7:0] 0 Pull-up or pull-down device is disabled.
1 Either a pull-up or pull-down device is enabled.
MC9S12XDP512 Data Sheet, Rev. 2.21
846
Freescale Semiconductor