MC9S12XD256MAL Datasheet, PDF (757/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 20 S12X Debug (S12XDBGV3) Module
20.3.2.7.1 Debug State Control Register 1 (DBGSCR1)
Address: 0x0027
7
6
5
4
R
0
0
0
0
W
Reset
0
0
0
0
= Unimplemented or Reserved
3
SC3
0
2
SC2
0
1
SC1
0
0
SC0
0
Figure 20-9. Debug State Control Register 1 (DBGSCR1)
Read: Anytime
Write: Anytime when S12XDBG not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 00. The state control register 1 selects the
targeted next state whilst in State1. The matches refer to the match channels of the comparator match
control logic as depicted in Figure 20-1 and described in Section 20.3.2.8.1”. Comparators must be
enabled by setting the comparator enable bit in the associated DBGXCTL control register.
Table 20-20. DBGSCR1 Field Descriptions
Field
3–0
SC[3:0]
Description
These bits select the targeted next state whilst in State1, based upon the match event.
Table 20-21. State1 Sequencer Next State Selection
SC[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Description
Any match triggers to state2
Any match triggers to state3
Any match triggers to Final State
Match2 triggers to State2....... Other matches have no effect
Match2 triggers to State3....... Other matches have no effect
Match2 triggers to Final State....... Other matches have no effect
Match0 triggers to State2....... Match1 triggers to State3....... Other matches have no effect
Match1 triggers to State3....... Match0 triggers Final State....... Other matches have no effect
Match0 triggers to State2....... Match2 triggers to State3....... Other matches have no effect
Match2 triggers to State3....... Match0 triggers Final State....... Other matches have no effect
Match1 triggers to State2....... Match3 triggers to State3....... Other matches have no effect
Match3 triggers to State3....... Match1 triggers to Final State....... Other matches have no effect
Match3 has no effect....... All other matches (M0,M1,M2) trigger to State2
Reserved
Reserved
Reserved
The trigger priorities described in Table 20-38 dictate that in the case of simultaneous matches, the match
on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to
final state has priority over all other matches.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
759