MC9S12XD256MAL Datasheet, PDF (329/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
7.3.2.13 Main Timer Interrupt Flag 2 (TFLG2)
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
TOF
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-18. Main Timer Interrupt Flag 2 (TFLG2)
Read: Anytime
Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not
affect the current status of the bit.
NOTE
When TFFCA = 1, the flag cannot be cleared via the normal flag clearing
mechanism (writing a one to the flag). Reference Section 7.3.2.6, “Timer
System Control Register 1 (TSCR1)”.
All bits reset to zero.
TFLG2 indicates when interrupt conditions have occurred. The flag can be cleared via the normal flag
clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (Reference TFFCA
bit in Section 7.3.2.6, “Timer System Control Register 1 (TSCR1)”).
Table 7-17. TFLG2 Field Descriptions
Field
7
TOF
Description
Timer Overflow Flag — Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
329