MC9S12XD256MAL Datasheet, PDF (517/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 12 Serial Peripheral Interface (S12SPIV4)
SPI
2
SPI Control Register 1
2
SPI Control Register 2
BIDIROE
SPC0
SPI
Interrupt
Request
SPI Status Register
SPIF MODF SPTEF
Interrupt Control
Baud Rate Generator
Counter
Slave
Control
CPOL
CPHA
Slave Baud Rate
Master Baud Rate
Master
Control
Phase + SCK In
Polarity
Control
Phase + SCK Out
Polarity
Control
Port
Control
Logic
Bus Clock
Prescaler Clock Select ^{Baud Rate}
SPPR 3 SPR 3
SPI Baud Rate Register
LSBFE=1
Shift
Clock
Shifter
LSBFE=0
Sample
Clock
Data In
SPI Data Register
8
LSBFE=1
8
MSB _{LSBFE=0 LSB}
LSBFE=0
LSBFE=1
Data Out
MOSI
SCK
SS
Figure 12-1. SPI Block Diagram
12.2 External Signal Description
This section lists the name and description of all ports including inputs and outputs that do, or may, connect
off chip. The SPI module has a total of four external pins.
12.2.1 MOSI — Master Out/Slave In Pin
This pin is used to transmit data out of the SPI module when it is configured as a master and receive data
when it is configured as slave.
12.2.2 MISO — Master In/Slave Out Pin
This pin is used to transmit data out of the SPI module when it is configured as a slave and receive data
when it is configured as master.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
517