MC9S12XD256MAL Datasheet, PDF (220/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 6 XGATE (S12XGATEV2)
AND
Logical AND
AND
Operation
RS1 & RS2 ⇒ RD
RD & IMM16 ⇒ RD (translates to ANDL RD, #IMM16[7:0]; ANDH RD, #IMM16[15:8])
Performs a bit wise logical AND of two 16 bit values and stores the result in the destination register RD.
Remark: There is no complement to the BITH and BITL functions. This can be imitated by using R0 as a
destination register. AND R0, RS1, RS2 performs a bit wise test without storing a result.
CCR Effects
NZVC
∆ ∆ 0—
N: Set if bit 15 of the result is set; cleared otherwise.
Z: Set if the result is $0000; cleared otherwise.
Refer to ANDH instruction for #IMM16 operations.
V: 0; cleared.
C: Not affected.
Code and CPU Cycles
Source Form
AND RD, RS1, RS2
AND RD, #IMM16
Address
Mode
TRI
IMM8
IMM8
00010
10000
10001
Machine Code
Cycles
RD
RS1
RS2 0 0
P
RD
IMM16[7:0]
P
RD
IMM16[15:8]
P
MC9S12XDP512 Data Sheet, Rev. 2.21
220
Freescale Semiconductor