MC9S12XD256MAL Datasheet, PDF (400/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 9 Inter-Integrated Circuit (IICV2) Block Description
Table 9-4. Multiplier Factor
IBC7-6
00
01
10
11
MUL
01
02
04
RESERVED
The number of clocks from the falling edge of SCL to the first tap (Tap[1]) is defined by the values shown
in the scl2tap column of Table 9-3, all subsequent tap points are separated by 2^IBC5-3 as shown in the
tap2tap column in Table 9-3. The SCL Tap is used to generated the SCL period and the SDA Tap is used
to determine the delay from the falling edge of SCL to SDA changing, the SDA hold time.
IBC7–6 defines the multiplier factor MUL. The values of MUL are shown in the Table 9-4.
SCL Divider
SCL
SDA
SDA Hold
SDA
SCL
SCL Hold(start)
SCL Hold(stop)
START condition
STOP condition
Figure 9-5. SCL Divider and SDA Hold
The equation used to generate the divider values from the IBFD bits is:
SCL Divider = MUL x {2 x (scl2tap + [(SCL_Tap -1) x tap2tap] + 2)}
MC9S12XDP512 Data Sheet, Rev. 2.21
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Freescale Semiconductor