MC9S12XD256MAL Datasheet, PDF (1272/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Appendix A Electrical Characteristics
A.7 SPI Timing
This section provides electrical parametrics and ratings for the SPI. In Table A-25 the measurement
conditions are listed.
Table A-25. Measurement Conditions
Description
Value
Unit
Drive mode
Full drive mode
—
Load capacitance C_LOAD1, on all outputs
50
pF
Thresholds for delay measurement points
(20% / 80%) V_DDX
V
1 _{Timing specified for equal load on all SPI output pins. Avoid asymmetric load.}
A.7.1 Master Mode
In Figure A-6 the timing diagram for master mode with transmission format CPHA = 0 is depicted.
SS1
(Output)
SCK
(CPOL = 0)
(Output)
SCK
(CPOL = 1)
(Output)
MISO
(Input)
MOSI
(Output)
2
1
12
4
4
12
5
6
MSB IN2
10
MSB OUT2
Bit 6 . . . 1
9
Bit 6 . . . 1
13
3
13
LSB IN
11
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure A-6. SPI Master Timing (CPHA = 0)
In Figure A-7 the timing diagram for master mode with transmission format CPHA=1 is depicted.
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MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor