MC9S12XD256MAL Datasheet, PDF (616/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 17 Memory Mapping Control (S12XMMCV2)
17.3 Memory Map and Registers
17.3.1 Module Memory Map
A summary of the registers associated with the MMC block is shown in Figure 1-2. Detailed descriptions
of the registers and bits are given in the subsections that follow.
Address
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x000A MMCCTL0 R
0
0
0
0
CS3E
CS2E
CS1E
CS0E
W
0x000B
MODE
R
0
0
0
0
0
MODC MODB MODA
W
0x0010
GPAGE
R
0
W
GP6
GP5
GP4
GP3
GP2
GP1
GP0
0x0011 DIRECT R
DP15
DP14
DP13
DP12
DP11
DP10
DP9
DP8
W
0x0012 Reserved R
0
0
0
0
0
0
0
0
W
0x0013 MMCCTL1 R
0
0
0
0
0
EROMON ROMHM ROMON
W
0x0014 Reserved R
0
0
0
0
0
0
0
0
W
0x0015 Reserved R
0
0
0
0
0
0
0
0
W
0x0016
RPAGE
R
RP7
RP6
RP5
RP4
RP3
RP2
RP1
RP0
W
0x0017
EPAGE
R
EP7
EP6
EP5
EP4
EP3
EP2
EP1
EP0
W
0x0030
PPAGE
R
PIX7
W
PIX6
PIX5
PIX4
PIX3
PIX2
PIX1
PIX0
0x0031 Reserved R
0
0
0
0
0
0
0
0
W
= Unimplemented or Reserved
Figure 17-2. MMC Register Summary
MC9S12XDP512 Data Sheet, Rev. 2.21
616
Freescale Semiconductor