MC9S12XD256MAL Datasheet, PDF (664/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 18 Memory Mapping Control (S12XMMCV3)
Table 18-11. Data Sources when CPU or BDM is Accessing Flash Area
Chip Modes
ROMON
EROMON
DATA SOURCE¹
Stretch²
Normal Single Chip
X
X
Internal Flash
N
Special Single Chip
Emulation Single Chip
X
0
Emulation Memory
N
X
1
Internal Flash
Normal Expanded
0
X
External Application
Y
1
X
Internal Flash
N
Emulation Expanded
0
X
External Application
Y
1
0
Emulation Memory
N
1
1
Internal Flash
Special Test
0
X
External Application
N
1
X
Internal Flash
1 _{Internal Flash means Flash resources inside the MCU are read/written.}
Emulation memory means resources inside the emulator are read/written (PRU registers, flash
replacement, RAM, EEPROM and register space are always considered internal).
External application means resources residing outside the MCU are read/written.
2 _{The external access stretch mechanism is part of the EBI module (refer to EBI Block Guide for details).}
18.3.2.6 RAM Page Index Register (RPAGE)
Address: 0x0016
R
W
Reset
7
RP7
1
6
RP6
1
5
RP5
1
4
RP4
1
3
RP3
1
2
RP2
1
1
RP1
0
0
RP0
1
Figure 18-11. RAM Page Index Register (RPAGE)
Read: Anytime
Write: Anytime
These eight index bits are used to page 4 KByte blocks into the RAM page window located in the local
(CPU or BDM) memory map from address 0x1000 to address 0x1FFF (see Figure 18-12). This supports
accessing up to 1022 Kbytes of RAM (in the Global map) within the 64 KByte Local map. The RAM page
index register is effectively used to construct paged RAM addresses in the Local map format.
CAUTION
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
MC9S12XDP512 Data Sheet, Rev. 2.21
664
Freescale Semiconductor