MC9S12XD256MAL Datasheet, PDF (84/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 2 Clocks and Reset Generator (S12CRGV6)
2.3.2 Register Descriptions
This section describes in address order all the CRG registers and their individual bits.
Register
Name
Bit 7
SYNR
R
0
W
6
5
4
3
2
1
Bit 0
0
SYN5
SYN4
SYN3
SYN2
SYN1
SYN0
REFDV
R
0
W
0
REFDV5 REFDV4 REFDV3 REFDV2 REFDV1 REFDV0
CTFLG
R
0
0
0
0
0
0
0
0
W
CRGFLG R
RTIF
W
CRGINT R
RTIE
W
PORF
ILAF
LVRF
0
LOCKIF
LOCKIE
LOCK
0
TRACK
SCMIF
0
SCMIE
SCM
0
CLKSEL R
0
PLLSEL
PSTP
W
0
0
PLLWAI
RTIWAI COPWAI
PLLCTL R
CME
W
PLLON
AUTO
ACQ
FSTWKP
PRE
PCE
SCME
RTICTL
R
RTDEC
W
RTR6
RTR5
RTR4
RTR3
RTR2
RTR1
RTR0
COPCTL R
0
0
WCOP
RSBCK
W
WRTMASK
0
CR2
CR1
CR0
FORBYP R
0
0
0
0
0
0
0
0
W
CTCTL
R
1
0
0
0
0
0
0
0
W
ARMCOP R
W
0
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
= Unimplemented or Reserved
Figure 2-3. S12CRGV6 Register Summary
MC9S12XDP512 Data Sheet, Rev. 2.21
84
Freescale Semiconductor