MC9S12XD256MAL Datasheet, PDF (261/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

LDW
Load Word from Memory
Chapter 6 XGATE (S12XGATEV2)
LDW
Operation
M[RB, #OFFS5] ⇒ RD
M[RB, RI] ⇒ RD
M[RB, RI] ⇒ RD; RI+2 ⇒ RI¹
RI-2 ⇒ RI; M[RS, RI] ⇒ RD
IMM16 ⇒ RD (translates to LDL RD, #IMM16[7:0]; LDH RD, #IMM16[15:8])
Loads a 16 bit value into the register RD.
CCR Effects
NZVC
————
N: Not affected.
Z: Not affected.
V: Not affected.
C: Not affected.
Code and CPU Cycles
Source Form
LDW RD, (RB, #OFFS5)
LDW RD, (RB, RI)
LDW RD, (RB, RI+)
LDW RD, (RB, -RI)
LDW RD, #IMM16
Address
Mode
IDO5
IDR
IDR+
-IDR
IMM8
IMM8
01001
01101
01101
01101
11110
11111
Machine Code
Cycles
RD
RB
OFFS5
PR
RD
RB
RI 0 0 PR
RD
RB
RI 0 1 PR
RD
RB
RI 1 0 PR
RD
IMM16[7:0]
P
RD
IMM16[15:8]
P
1. If the same general purpose register is used as index (RI) and destination register (RD), the content of the register will not be
incremented after the data move: M[RB, RI] ⇒ RD
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
261