MC9S12XD256MAL Datasheet, PDF (937/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

23.0.5.31 Port M Input Register (PTIM)
7
R PTIM7
6
PTIM6
5
PTIM5
4
PTIM4
3
PTIM3
2
PTIM2
1
PTIM1
0
PTIM0
W
Reset¹
—
—
—
—
—
—
—
—
= Unimplemented or Reserved
Figure 23-33. Port M Input Register (PTIM)
1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the
associated pin values.
Read: Anytime.
Write: Never, writes to this register have no effect.
This register always reads back the buffered state of the associated pins. This can also be used to
detect overload or short circuit conditions on output pins.
23.0.5.32 Port M Data Direction Register (DDRM)
7
R
DDRM7
W
6
DDRM6
5
DDRM5
4
DDRM4
3
DDRM3
2
DDRM2
1
DDRM1
0
DDRM0
Reset
0
0
0
0
0
0
0
0
Figure 23-34. Port M Data Direction Register (DDRM)
Read: Anytime.
Write: Anytime.
This register configures each port M pin as either input or output.
The CAN forces the I/O state to be an output for each port line associated with an enabled output
(TXCAN). also forces the I/O state to be an input for each port line associated with an enabled
input (RXCAN). In those cases the data direction bits will not change.
The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral
module is disabled.
Table 23-33. DDRM Field Descriptions
Field
Description
7–0
DDRM[7:0]
Data Direction Port M
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PTM or PTIM registers, when changing the DDRM register.