MC9S12XD256MAL Datasheet, PDF (218/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 6 XGATE (S12XGATEV2)
ADDH
Add Immediate 8 bit Constant
(High Byte)
ADDH
Operation
RD + IMM8:$00 ⇒ RD
Adds the content of high byte of register RD and a signed immediate 8 bit constant using binary addition
and stores the result in the high byte of the destination register RD. This instruction can be used after an
ADDL for a 16 bit immediate addition.
Example:
ADDL
ADDH
R2,#LOWBYTE
R2,#HIGHBYTE
; R2 = R2 + 16 bit immediate
CCR Effects
NZVC
∆∆∆∆
N: Set if bit 15 of the result is set; cleared otherwise.
Z: Set if the result is $0000; cleared otherwise.
V: Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RD[15]_old & IMM8[7] & RD[15]_new | RD[15]_old & IMM8[7] & RD[15]_new
C: Set if there is a carry from the bit 15 of the result; cleared otherwise.
RD[15]_old & IMM8[7] | RD[15]_old & RD[15]_new | IMM8[7] & RD[15]_new
Code and CPU Cycles
Source Form
ADDH RD, #IMM8
Address
Mode
IMM8
11101
Machine Code
RD
IMM8
Cycles
P
MC9S12XDP512 Data Sheet, Rev. 2.21
218
Freescale Semiconductor