MC9S12XD256MAL Datasheet, PDF (348/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
7.3.2.30 Modulus Down-Counter Count Register (MCCNT)
R
W
Reset
15
MCCNT15
1
14
MCCNT14
1
13
MCCNT13
1
12
MCCNT12
1
11
MCCNT11
1
10
MCCNT10
1
9
MCCNT9
1
Figure 7-55. Modulus Down-Counter Count Register High (MCCNT)
8
MCCNT8
1
R
W
Reset
7
MCCNT7
6
MCCNT6
5
MCCNT5
4
MCCNT4
3
MCCNT3
2
MCCNT2
1
MCCNT1
1
1
1
1
1
1
1
Figure 7-56. Modulus Down-Counter Count Register Low (MCCNT)
0
MCCNT9
1
Read: Anytime
Write: Anytime.
All bits reset to one.
A full access for the counter register will take place in one clock cycle.
NOTE
A separate read/write for high byte and low byte will give different results
than accessing them as a word.
If the RDMCL bit in MCCTL register is cleared, reads of the MCCNT register will return the present value
of the count register. If the RDMCL bit is set, reads of the MCCNT will return the contents of the load
register.
If a 0x0000 is written into MCCNT when LATQ and BUFEN in ICSYS register are set, the input capture
and pulse accumulator registers will be latched.
With a 0x0000 write to the MCCNT, the modulus counter will stay at zero and does not set the MCZF flag
in MCFLG register.
If the modulus down counter is enabled (MCEN = 1) and modulus mode is enabled (MODMC = 1), a write
to MCCNT will update the load register with the value written to it. The count register will not be updated
with the new value until the next counter underflow.
If modulus mode is not enabled (MODMC = 0), a write to MCCNT will clear the modulus prescaler and
will immediately update the counter register with the value written to it and down-counts to 0x0000 and
stops.
The FLMC bit in MCCTL can be used to immediately update the count register with the new value if an
immediate load is desired.
MC9S12XDP512 Data Sheet, Rev. 2.21
348
Freescale Semiconductor