MC9S12XD256MAL Datasheet, PDF (265/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

NEG
Two’s Complement
Chapter 6 XGATE (S12XGATEV2)
NEG
Operation
–RS ⇒ RD (translates to SUB RD, R0, RS)
–RD ⇒ RD (translates to SUB RD, R0, RD)
Performs a two’s complement on a general purpose register.
CCR Effects
NZVC
∆∆∆∆
N: Set if bit 15 of the result is set; cleared otherwise.
Z: Set if the result is $0000; cleared otherwise.
V: Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RS[15] & RD[15]_new
C: Set if there is a carry from the bit 15 of the result; cleared otherwise
RS[15] | RD[15]_new
Code and CPU Cycles
Source Form
NEG RD, RS
NEG RD
Address
Mode
Machine Code
TRI 0 0 0 1 1 RD 0 0 0 RS
TRI 0 0 0 1 1 RD 0 0 0 RD
Cycles
00 P
00 P
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
265