MC9S12XD256MAL Datasheet, PDF (641/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 17 Memory Mapping Control (S12XMMCV2)
The following conditions must be satisfied to ensure correct operation of the RAM protection mechanism:
• Value stored in RAMXGU must be lower than the value stored in RAMSHL.
• Value stored RAMSHL must be lower or equal than the value stored in RAMSHU.
Table 17-21. RAM Write Protection Interrupt Vectors
Interrupt Source
CPU access violation
CCR Mask
I Bit
Local Enable
AVIE in RAMWPC
$00_0000
$00_0800
2K Registers
Unimplemented
$0F_RAMXGU_FF
XGATE RAM
Region
$0F_RAMSHL_00
Shared Region
$0F_RAMSHU_FF
Only XGATE is allowed to write
Only CPU is allowed to write
CPU and XGATE are allowed to write
Only CPU is allowed to write
$0F_FFFF
Figure 17-25. RAM Write Protection Scheme
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
641