MC9S12XD256MAL Datasheet, PDF (766/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 20 S12X Debug (S12XDBGV3) Module
20.3.2.8.8 Debug Comparator Data Low Mask Register (DBGXDLM)
Address: 0x002F
R
W
Reset
7
Bit 7
0
6
Bit 6
0
5
Bit 5
0
4
Bit 4
0
3
Bit 3
0
2
Bit 2
0
1
Bit 1
0
0
Bit 0
0
Figure 20-21. Debug Comparator Data Low Mask Register (DBGXDLM)
Read: Anytime
Write: Anytime when S12XDBG not armed.
Table 20-35. DBGXDLM Field Descriptions
Field
7–0
Bits[7:0]
Description
Comparator Data Low Mask Bits — The Comparator data low mask bits control whether the selected
comparator compares the data bus bits [7:0] to the corresponding comparator data compare bits. This register
is available only for comparators A and C.
0 Do not compare corresponding data bit
1 Compare corresponding data bit
20.4 Functional Description
This section provides a complete functional description of the S12XDBG module. If the part is in secure
mode, the S12XDBG module can generate breakpoints but tracing is not possible.
20.4.1 S12XDBG Operation
Arming the S12XDBG module by setting ARM in DBGC1 allows triggering, and storing of data in the
trace buffer and can be used to cause breakpoints to the S12XCPU or the XGATE module. The DBG
module is made up of four main blocks, the comparators, control logic, the state sequencer, and the trace
buffer.
The comparators monitor the bus activity of the S12XCPU and XGATE modules. Comparators can be
configured to monitor address and databus. Comparators can also be configured to mask out individual
data bus bits during a compare and to use R/W and word/byte access qualification in the comparison. When
a match with a comparator register value occurs the associated control logic can trigger the state sequencer
to another state (see Figure 20-23). Either forced or tagged triggers are possible. Using a forced trigger,
the trigger is generated immediately on a comparator match. Using a tagged trigger, at a comparator match,
the instruction opcode is tagged and only if the instruction reaches the execution stage of the instruction
queue is a trigger generated. In the case of a transition to Final State, bus tracing is triggered and/or a
breakpoint can be generated. Tracing of both S12XCPU and/or XGATE bus activity is possible.
Independent of the state sequencer, a breakpoint can be triggered by the external TAGHI / TAGLO signals,
by an XGATE S/W breakpoint request or by writing to the TRIG bit in the DBGC1 control register.
MC9S12XDP512 Data Sheet, Rev. 2.21
768
Freescale Semiconductor