MC9S12XD256MAL Datasheet, PDF (1023/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port
register, otherwise the value at the pins is read.
24.0.5.59 Port AD1 Data Register 1 (PT1AD1)
7
R
PT1AD17
W
6
PT1AD16
5
PT1AD15
4
PT1AD14
3
PT1AD13
2
PT1AD12
1
PT1AD11
0
PT1AD10
Reset
0
0
0
0
0
0
0
0
Figure 24-61. Port AD1 Data Register 1 (PT1AD1)
Read: Anytime.
Write: Anytime.
This register is associated with AD1 pins PAD[7:0]. These pins can also be used as general purpose
I/O.
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port
register, otherwise the value at the pins is read.
24.0.5.60 Port AD1 Data Direction Register 0 (DDR0AD1)
7
6
5
4
3
2
1
R
DDR0AD115 DDR0AD114 DDR0AD113 DDR0AD112 DDR0AD111 DDR0AD110 DDR0AD19
W
0
DDR0AD18
Reset
0
0
0
0
0
0
0
0
Figure 24-62. Port AD1 Data Direction Register 0 (DDR0AD1)
Read: Anytime.
Write: Anytime.
This register configures pin PAD[15:8] as either input or output.
Table 24-54. DDR0AD1 Field Descriptions
Field
Description
7–0
DDR0AD1[15:8]
Data Direction Port AD1 Register 0
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is
read on PTAD10 register, when changing the DDR0AD1 register.
Note: To use the digital input function on Port AD1 the ATD1 digital input enable register (ATD1DIEN0) has
to be set to logic level “1”.