MC9S12XD256MAL Datasheet, PDF (699/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 19 S12X Debug (S12XDBGV2) Module
19.3.1.3 Debug Trace Control Register (DBGTCR)
0x0022
R
W
Reset
7
6
TSOURCE
5
4
TRANGE
3
2
TRCMOD
0
0
0
0
0
0
Figure 19-5. Debug Trace Control Register (DBGTCR)
Read: Anytime
Write: Bits 7:6 only when DBG is neither secure nor armed.
Bits 5:0 anytime the module is disarmed.
Table 19-8. DBGTCR Field Descriptions
1
0
TALIGN
0
0
Field
Description
7–6
Trace Source Control Bits — The TSOURCE bits select the data source for the tracing session. If the MCU
TSOURCE system is secured, these bits cannot be set and tracing is inhibited. See Table 19-9.
5–4
Trace Range Bits —The TRANGE bits allow filtering of trace information from a selected address range when
TRANGE[5:4] tracing from the CPU in detail mode. The XGATE tracing range cannot be narrowed using these bits. To use a
comparator for range filtering, the corresponding COMPE and SRC bits must remain cleared. If the COMPE bit
is not clear then the comparator will also be used to generate state sequence triggers or tags. If the SRC bit is
set the comparator is mapped to the XGATE busses, corrupting the trace. See Table 19-10.
3–2
Trace Mode Bits — See Section 19.4.5.2, “Trace Modes“ for detailed trace mode descriptions. In normal
TRCMOD[3:2] mode, change of flow information is stored. In loop1 mode, change of flow information is stored but redundant
entries into trace memory are inhibited. In detail mode, address and data for all memory and register accesses
is stored. See Table 19-11
1–0
Trigger Align Bits — These bits control whether the trigger is aligned to the beginning, end or the middle of a
TALIGN[1:0] tracing session. See Table 19-12.
Table 19-9. TSOURCE Trace Source Bit Encoding
TSOURCE
Tracing Source
00
No tracing requested
01
10¹
11^{1, 2}
CPU
XGATE
Both CPU and XGATE
1 _{No range limitations are allowed. Thus tracing operates as if TRANGE = 00.}
2 _{No detail mode tracing supported. If TRCMOD =10, no information is stored.}
Table 19-10. TRANGE Trace Range Encoding
TRANGE
00
01
10
Tracing Source
Trace from all addresses (No filter)
Trace only in address range from 0x0000 to comparator D
Trace only in address range from comparator C to 0x7FFFFF
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
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