MC9S12XD256MAL Datasheet, PDF (1010/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
24.0.5.34 Port P Data Register (PTP)
R
W
PWM
SPI
Reset
7
PTP7
PWM7
0
6
PTP6
5
PTP5
4
PTP4
3
PTP3
2
PTP2
PWM6
0
PWM5
PWM4
PWM3
PWM2
SS1
SCK1
0
0
0
0
Figure 24-36. Port P Data Register (PTP)
1
PTP1
PWM1
MOSI1
0
0
PTP0
PWM0
MISO1
0
Read: Anytime.
Write: Anytime.
Port P pins 7–0 are associated with the PWM as well as the SPI1. These pins can be used as general
purpose I/O when not used with any of the peripherals.
If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the
port register, otherwise the buffered pin input state is read.
The PWM function takes precedence over the general purpose I/O and the SPI1 function if the associated
PWM channel is enabled. While channels 6-0 are output only if the respective channel is enabled, channel
7 can be PWM output or input if the shutdown feature is enabled. Refer to PWM section for details.
The SPI1 function takes precedence over the general purpose I/O function if enabled. Refer to SPI section
for details.
24.0.5.35 Port P Input Register (PTIP)
7
R PTIP7
6
PTIP6
5
PTIP5
4
PTIP4
3
PTIP3
2
PTIP2
1
PTIP1
0
PTIP0
W
Reset¹
—
—
—
—
—
—
—
—
= Unimplemented or Reserved
Figure 24-37. Port P Input Register (PTIP)
1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the
associated pin values.
Read: Anytime.
Write: Never, writes to this register have no effect.
This register always reads back the buffered state of the associated pins. This can also be used to detect
overload or short circuit conditions on output pins.
1012
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor