MC9S12XD256MAL Datasheet, PDF (1068/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 25 2 Kbyte EEPROM Module (S12XEETX2KV1)
25.6.1 Unsecuring the MCU in Special Single Chip Mode using BDM
Before the MCU can be unsecured in special single chip mode, the EEPROM memory must be erased
using the following method :
• Reset the MCU into special single chip mode, delay while the erase test is performed by the BDM
secure ROM, send BDM commands to disable protection in the EEPROM module, and execute a
mass erase command write sequence to erase the EEPROM memory.
After the CCIF flag sets to indicate that the EEPROM mass operation has completed and assuming that the
Flash memory has also been erased, reset the MCU into special single chip mode. The BDM secure ROM
will verify that the Flash and EEPROM memory are erased and will assert the UNSEC bit in the BDM
status register. This BDM action will cause the MCU to override the Flash security state and the MCU will
be unsecured. Once the MCU is unsecured, BDM commands will be enabled and the Flash security byte
may be programmed to the unsecure state.
25.7 Resets
25.7.1 EEPROM Reset Sequence
On each reset, the EEPROM module executes a reset sequence to hold CPU activity while loading the
EPROT register from the EEPROM memory according to Table 25-1.
25.7.2 Reset While EEPROM Command Active
If a reset occurs while any EEPROM command is in progress, that command will be immediately aborted.
The state of a word being programmed or the sector / block being erased is not guaranteed.
25.8 Interrupts
The EEPROM module can generate an interrupt when all EEPROM command operations have completed,
when the EEPROM address, data, and command buffers are empty.
Table 25-10. EEPROM Interrupt Sources
Interrupt Source
EEPROM address, data, and command buffers empty
All EEPROM commands completed
Interrupt Flag
CBEIF
(ESTAT register)
CCIF
(ESTAT register)
Local Enable
CBEIE
(ECNFG register)
CCIE
(ECNFG register)
Global (CCR) Mask
I Bit
I Bit
NOTE
Vector addresses and their relative interrupt priority are determined at the
MCU level.
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MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor