MC9S12XD256MAL Datasheet, PDF (553/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 13 Periodic Interrupt Timer (S12PIT24B4CV1)
is set, an interrupt service is requested whenever the corresponding time-out flag PTF in the PIT time-out
flag (PITTF) register is set. The flag can be cleared by writing a one to the flag bit.
NOTE
Be careful when resetting the PITE, PINTE or PITCE bits in case of pending
PIT interrupt requests, to avoid spurious interrupt requests.
13.4.3 Hardware Trigger
The PIT module contains four hardware trigger signal lines PITTRIG[3:0], one for each timer channel.
These signals can be connected on SoC level to peripheral modules enabling e.g. periodic ATD conversion
(please refer to the SoC Guide for the mapping of PITTRIG[3:0] signals to peripheral modules).
Whenever a timer channel time-out is reached, the corresponding PTF flag is set and the corresponding
trigger signal PITTRIG triggers a rising edge. The trigger feature requires a minimum time-out period of
two bus clock cycles because the trigger is asserted high for at least one bus clock cycle. For load register
values PITLD = 0x0001 and PITMTLD = 0x0002 the flag setting, trigger timing and a restart with force
load is shown in Figure 13-20.
13.5 Initialization/Application Information
13.5.1 Startup
Set the configuration registers before the PITE bit in the PITCFLMT register is set. Before PITE is set, the
configuration registers can be written in arbitrary order.
13.5.2 Shutdown
When the PITCE register bits, the PITINTE register bits or the PITE bit in the PITCFLMT register are
cleared, the corresponding PIT interrupt flags are cleared. In case of a pending PIT interrupt request, a
spurious interrupt can be generated. Two strategies, which avoid spurious interrupts, are recommended:
1. Reset the PIT interrupt flags only in an ISR. When entering the ISR, the I mask bit in the CCR is
set automatically. The I mask bit must not be cleared before the PIT interrupt flags are cleared.
2. After setting the I mask bit with the SEI instruction, the PIT interrupt flags can be cleared. Then
clear the I mask bit with the CLI instruction to re-enable interrupts.
13.5.3 Flag Clearing
A flag is cleared by writing a one to the flag bit. Always use store or move instructions to write a one in
certain bit positions. Do not use the BSET instructions. Do not use any C-constructs that compile to BSET
instructions. “BSET flag_register, #mask” must not be used for flag clearing because BSET is a
read-modify-write instruction which writes back the “bit-wise or” of the flag_register and the mask into
the flag_register. BSET would clear all flag bits that were set, independent from the mask.
For example, to clear flag bit 0 use: MOVB #$01,PITTF.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
553