MC9S12XD256MAL Datasheet, PDF (115/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 2 Clocks and Reset Generator (S12CRGV6)
2.5.2 Clock Monitor Reset
The CRG generates a clock monitor reset in case all of the following conditions are true:
• Clock monitor is enabled (CME = 1)
• Loss of clock is detected
• Self-clock mode is disabled (SCME = 0).
The reset event asynchronously forces the configuration registers to their default settings (see Section 2.3,
“Memory Map and Register Definition”). In detail the CME and the SCME are reset to logical ‘1’ (which
doesn’t change the state of the CME bit, because it has already been set). As a consequence the CRG
immediately enters self clock mode and starts its internal reset sequence. In parallel the clock quality check
starts. As soon as clock quality check indicates a valid oscillator clock the CRG switches to OSCCLK and
leaves self clock mode. Since the clock quality checker is running in parallel to the reset generator, the
CRG may leave self clock mode while still completing the internal reset sequence. When the reset
sequence is finished, the CRG checks the internally latched state of the clock monitor fail circuit. If a clock
monitor fail is indicated, processing begins by fetching the clock monitor reset vector.
2.5.3 Computer Operating Properly Watchdog (COP) Reset
When COP is enabled, the CRG expects sequential write of 0x_55 and 0x_AA (in this order) to the
ARMCOP register during the selected time-out period. Once this is done, the COP time-out period restarts.
If the program fails to do this the CRG will generate a reset. Also, if any value other than 0x_55 or 0x_AA
is written, the CRG immediately generates a reset. In case windowed COP operation is enabled writes
(0x_55 or 0x_AA) to the ARMCOP register must occur in the last 25% of the selected time-out period. A
premature write the CRG will immediately generate a reset.
As soon as the reset sequence is completed the reset generator checks the reset condition. If no clock
monitor failure is indicated and the latched state of the COP timeout is true, processing begins by fetching
the COP vector.
2.5.4 Power On Reset, Low Voltage Reset
The on-chip voltage regulator detects when V_DD to the MCU has reached a certain level and asserts power
on reset or low voltage reset or both. As soon as a power on reset or low voltage reset is triggered the CRG
performs a quality check on the incoming clock signal. As soon as clock quality check indicates a valid
oscillator clock signal, the reset sequence starts using the oscillator clock. If after 50 check windows the
clock quality check indicated a non-valid oscillator clock, the reset sequence starts using self-clock mode.
Figure 2-26 and Figure 2-27 show the power-up sequence for cases when the RESET pin is tied to V_DD
and when the RESET pin is held low.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
115