MC9S12XD256MAL Datasheet, PDF (205/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 6 XGATE (S12XGATEV2)
Figure 6-22 gives an example of the typical usage of the XGATE hardware semaphores.
Two concurrent threads are running on the system. One is running on the S12X_CPU and the other is
running on the RISC core. They both have a critical section of code that accesses the same system resource.
To guarantee that the system resource is only accessed by one thread at a time, the critical code sequence
must be embedded in a semaphore lock/release sequence as shown.
S12X_CPU
.........
XGATE
.........
%1 ⇒ XGSEMx
SSEM
XGSEM ≡ %1?
BCC?
critical
code
sequence
critical
code
sequence
XGSEM ⇒ %0
CSEM
.........
.........
Figure 6-22. Algorithm for Locking and Releasing Semaphores
6.4.5 Software Error Detection
The XGATE module will immediately terminate program execution after detecting an error condition
caused by erratic application code. There are three error conditions:
• Execution of an illegal opcode
• Illegal vector or opcode fetches
• Illegal load or store accesses
All opcodes which are not listed in section Section 6.8, “Instruction Set” are illegal opcodes. Illegal vector
and opcode fetches as well as illegal load and store accesses are defined on chip level. Refer to the
S12X_MMC Section for a detailed information.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
205