MC9S12XD256MAL Datasheet, PDF (502/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 11 Serial Communication Interface (S12SCIV5)
11.4.6 Receiver
Internal Bus
SBR12:SBR0
SCI Data Register
SCRXD
From TXD Pin
or Transmitter
Bus
Clock
RXPOL
Loop
Control
LOOPS
RSRC
Baud Divider
Data
Recovery
RE
RAF
M
WAKE
ILT
PE
PT
Wakeup
Logic
Parity
Checking
BRKDFE
Break
Detect Logic
11-Bit Receive Shift Register
H8 7 6 5 4 3 2 1 0 L
RDRF
OR
BRKDIF
BRKDIE
FE
NF
RWU
PE
R8
IDLE
ILIE
Idle IRQ
RDRF/OR
IRQ
RIE
Break IRQ
Active Edge
Detect Logic
RXEDGIF
RXEDGIE
Figure 11-20. SCI Receiver Block Diagram
RX Active Edge IRQ
11.4.6.1 Receiver Character Length
The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI
control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in
SCI data register high (SCIDRH) is the ninth bit (bit 8).
11.4.6.2 Character Reception
During an SCI reception, the receive shift register shifts a frame in from the RXD pin. The SCI data register
is the read-only buffer between the internal data bus and the receive shift register.
After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the
SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCISR1) becomes set,
MC9S12XDP512 Data Sheet, Rev. 2.21
502
Freescale Semiconductor