MC9S12XD256MAL Datasheet, PDF (938/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
23.0.5.33 Port M Reduced Drive Register (RDRM)
R
W
Reset
7
RDRM7
0
6
RDRM6
5
RDRM5
4
RDRM4
3
RDRM3
2
RDRM2
0
0
0
0
0
Figure 23-35. Port M Reduced Drive Register (RDRM)
1
RDRM1
0
0
RDRM0
0
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each Port M output pin as either full or reduced. If the port
is used as input this bit is ignored.
Table 23-34. RDRM Field Descriptions
Field
Description
7–0
Reduced Drive Port M
RDRM[7:0] 0 Full drive strength at output.
1 Associated pin drives at about 1/6 of the full drive strength.
23.0.5.34 Port M Pull Device Enable Register (PERM)
R
W
Reset
7
PERM7
0
6
PERM6
5
PERM5
4
PERM4
3
PERM3
2
PERM2
1
PERM1
0
0
0
0
0
0
Figure 23-36. Port M Pull Device Enable Register (PERM)
0
PERM0
0
Read: Anytime.
Write: Anytime.
This register configures whether a pull-up or a pull-down device is activated, if the port is used as input or
wired-OR output. This bit has no effect if the port is used as push-pull output. Out of reset no pull device
is enabled.
Table 23-35. PERM Field Descriptions
Field
Description
7–0
Pull Device Enable Port M
PERM[7:0] 0 Pull-up or pull-down device is disabled.
1 Either a pull-up or pull-down device is enabled.
MC9S12XDP512 Data Sheet, Rev. 2.21
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