MC9S12XD256MAL Datasheet, PDF (1196/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1)
7
6
5
4
3
2
1
0
R
0
W
MRDS
0
0
0
0
0
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 29-6. Flash Test Mode Register (FTSTMOD)
MRDS bits are readable and writable while all remaining bits read 0 and are not writable in normal mode.
Table 29-6. FTSTMOD Field Descriptions
Field
Description
6:5
Margin Read Setting — The MRDS[1:0] bits are used to set the sense-amp margin level for reads of the Flash
MRDS[1:0] array as shown in Table 29-7.
Table 29-7. FTSTMOD Margin Read Settings
MRDS[1:0]
Margin Read Setting
00
Normal
01
Program Margin¹
10
Erase Margin²
11
Normal
1 Flash array reads will be sensitive to program margin.
2 Flash array reads will be sensitive to erase margin.
29.3.2.4 Flash Configuration Register (FCNFG)
The FCNFG register enables the Flash interrupts and gates the security backdoor writes.
7
6
5
4
3
2
1
0
R
Undefined
0
0
0
0
CBEIE
CCIE
KEYACC
W
Reset
0
0
0
Undefined
0
0
0
0
= Unimplemented or Reserved
Figure 29-7. Flash Configuration Register (FCNFG)
CBEIE, CCIE and KEYACC bits are readable and writable while all remaining bits read 0 and are not
writable in normal mode. KEYACC is only writable if KEYEN (see Section 29.3.2.2, “Flash Security
Register (FSEC)” is set to the enabled state.
1198
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor