MC9S12XD256MAL Datasheet, PDF (345/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
Table 7-34. Precision Timer Modulus Counter Prescaler Select Examples when PRNT = 1 (continued)
PTMPS7
0
0
0
0
0
1
PTMPS6
0
0
0
0
1
1
PTMPS5
0
0
0
1
1
1
PTMPS4
0
0
1
1
1
1
PTMPS3
0
1
1
1
1
1
PTMPS2
1
1
1
1
1
1
PTMPS1
1
1
1
1
1
1
PTMPS0
1
1
1
1
1
1
Prescaler
Division
Rate
8
16
32
64
128
256
7.3.2.27 16-Bit Pulse Accumulator B Control Register (PBCTL)
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
PBEN
PBOVI
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-49. 16-Bit Pulse Accumulator B Control Register (PBCTL)
Read: Anytime
Write: Anytime
All bits reset to zero.
Table 7-35. PBCTL Field Descriptions
Field
6
PBEN
1
PBOVI
Description
Pulse Accumulator B System Enable — PBEN is independent from TEN. With timer disabled, the pulse
accumulator can still function unless pulse accumulator is disabled.
0 16-bit pulse accumulator system disabled. 8-bit PAC1 and PAC0 can be enabled when their related enable bits
in ICPAR are set.
1 Pulse accumulator B system enabled. The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form
the PACB 16-bit pulse accumulator B. When PACB is enabled, the PACN1 and PACN0 registers contents are
respectively the high and low byte of the PACB.
PA1EN and PA0EN control bits in ICPAR have no effect.
The PACB shares the input pin with IC0.
Pulse Accumulator B Overflow Interrupt Enable
0 Interrupt inhibited
1 Interrupt requested if PBOVF is set
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
345