MC9S12XD256MAL Datasheet, PDF (339/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
7.3.2.21 ICPAR — Input Control Pulse Accumulators Register (ICPAR)
7
6
5
4
R
0
0
0
0
W
Reset
0
0
0
0
= Unimplemented or Reserved
3
PA3EN
0
2
PA2EN
0
1
PA1EN
0
0
PA0EN
0
Figure 7-43. Input Control Pulse Accumulators Register (ICPAR)
Read: Anytime
Write: Anytime.
All bits reset to zero.
The 8-bit pulse accumulators PAC3 and PAC2 can be enabled only if PAEN in PACTL is cleared. If PAEN
is set, PA3EN and PA2EN have no effect.
The 8-bit pulse accumulators PAC1 and PAC0 can be enabled only if PBEN in PBCTL is cleared. If PBEN
is set, PA1EN and PA0EN have no effect.
Table 7-25. ICPAR Field Descriptions
Field
3:0
8-Bit Pulse Accumulator ‘x’ Enable
PA[3:0]EN 0 8-Bit Pulse Accumulator is disabled.
1 8-Bit Pulse Accumulator is enabled.
Description
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
339