MC9S12XD256MAL Datasheet, PDF (954/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with
Port J.
Table 23-56. PIEJ Field Descriptions
Field
Description
7–0
PIEJ[7:4]
PIEJ[2:0]
Interrupt Enable Port J
0 Interrupt is disabled (interrupt flag masked).
1 Interrupt is enabled.
23.0.5.61 Port J Interrupt Flag Register (PIFJ)
7
6
5
4
3
2
1
0
R
0
PIFJ7
PIFJ6
PIFJ5
PIFJ4
PIFJ2
PIFJ1
PIFJ0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 23-63. Port J Interrupt Flag Register (PIFJ)
Read: Anytime.
Write: Anytime.
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based
on the state of the PPSJ register. To clear this flag, write logic level “1” to the corresponding bit in the PIFJ
register. Writing a “0” has no effect.
Table 23-57. PIEJ Field Descriptions
Field
7–0
PIFJ[7:4]
PIFJ[2:0]
Description
Interrupt Flags Port J
0 No active edge pending. Writing a “0” has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
Writing a logic level “1” clears the associated flag.
23.0.5.62 Port AD0 Data Register 1 (PT1AD0)
7
R
PT1AD07
W
Reset
0
Read: Anytime.
Write: Anytime.
6
5
4
3
2
PT1AD06 PT1AD05 PT1AD04 PT1AD03 PT1AD02
0
0
0
0
0
Figure 23-64. Port AD0 Data Register 1 (PT1AD0)
1
PT1AD01
0
0
PT1AD00
0
MC9S12XDP512 Data Sheet, Rev. 2.21
956
Freescale Semiconductor