MC9S12XD256MAL Datasheet, PDF (1194/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1)
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
RESERVED1 R
0
0
0
0
0
0
0
0
W
RESERVED2 R
0
0
0
0
0
0
0
0
W
RESERVED3 R
0
0
0
0
0
0
0
0
W
RESERVED4 R
0
0
0
0
0
0
0
0
W
Figure 29-3. FTX128K1 Register Summary (continued)
29.3.2.1 Flash Clock Divider Register (FCLKDIV)
The FCLKDIV register is used to control timed events in program and erase algorithms.
R
W
Reset
7
FDIVLD
0
6
PRDIV8
5
FDIV5
4
FDIV4
3
FDIV3
2
FDIV2
0
0
0
0
0
= Unimplemented or Reserved
Figure 29-4. Flash Clock Divider Register (FCLKDIV)
1
FDIV1
0
0
FDIV0
0
All bits in the FCLKDIV register are readable, bits 6-0 are write once and bit 7 is not writable.
Table 29-2. FCLKDIV Field Descriptions
Field
Description
7
FDIVLD
6
PRDIV8
Clock Divider Loaded.
0 Register has not been written.
1 Register has been written to since the last reset.
Enable Prescalar by 8.
0 The oscillator clock is directly fed into the clock divider.
1 The oscillator clock is divided by 8 before feeding into the clock divider.
5:0
FDIV[5:0]
Clock Divider Bits — The combination of PRDIV8 and FDIV[5:0] must divide the oscillator clock down to a
frequency of 150 kHz–200 kHz. The maximum divide ratio is 512. Please refer to Section 29.4.1.1, “Writing the
FCLKDIV Register” for more information.
29.3.2.2 Flash Security Register (FSEC)
The FSEC register holds all bits associated with the security of the MCU and Flash module.
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MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor