MC9S12XD256MAL Datasheet, PDF (621/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

17.3.2.3
Global Page Index Register (GPAGE)
Chapter 17 Memory Mapping Control (S12XMMCV2)
Address: 0x0010
7
R
0
W
6
GP6
5
GP5
4
GP4
Reset
0
0
0
0
= Unimplemented or Reserved
3
GP3
0
2
GP2
0
1
GP1
0
0
GP0
0
Figure 17-6. Global Page Index Register (GPAGE)
Read: Anytime
Write: Anytime
The global page index register is used only when the CPU is executing a global instruction (GLDAA,
GLDAB, GLDD, GLDS, GLDX, GLDY,GSTAA, GSTAB, GSTD, GSTS, GSTX, GSTY) (see CPU Block
Guide). The generated global address is the result of concatenation of the CPU local address [15:0] with
the GPAGE register [22:16] (see Figure 1-7).
CAUTION
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
Global Address [22:0]
Bit22
Bit16 Bit15
Bit 0
GPAGE Register [6:0]
CPU Address [15:0]
Figure 17-7. GPAGE Address Mapping
Table 17-7. GPAGE Field Descriptions
Field
6–0
GP[6:0]
Description
Global Page Index Bits 6–0 — These page index bits are used to select which of the 128 64-kilobyte pages is
to be accessed.
Example 17-1. This example demonstrates usage of the GPAGE register
LDAADR
MOVB
GLDAA
EQU $5000
#$14, GPAGE
>LDAADR
;Initialize LDADDR to the value of $5000
;Initialize GPAGE register with the value of $14
;Load Accu A from the global address $14_5000
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
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