MC9S12XD256MAL Datasheet, PDF (1239/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Appendix A Electrical Characteristics
A.1.5 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima
is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the
device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either V_SS35 or V_DD35).
Table A-1. Absolute Maximum Ratings¹
Num
Rating
Symbol
Min
Max
Unit
1 I/O, regulator and analog supply voltage
2 Digital logic supply voltage²
3 PLL supply voltage²
4 Voltage difference V_DDX to V_DDR and V_DDA
5 Voltage difference V_SSX to V_SSR and V_SSA
6 Digital I/O input voltage
7 Analog reference
8 XFC, EXTAL, XTAL inputs
9 TEST input
10 Instantaneous maximum current
Single pin limit for all digital I/O pins³
V_DD35
V_DD
V_DDPLL
∆_VDDX
∆_VSSX
V_IN
V_RH, V_RL
V_ILV
V_TEST
I_D
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–25
6.0
V
3.0
V
3.0
V
0.3
V
0.3
V
6.0
V
6.0
V
3.0
V
10.0
V
+25
mA
11 Instantaneous maximum current
Single pin limit for XFC, EXTAL, XTAL⁴
I_DL
–25
+25
mA
12 Instantaneous maximum current
Single pin limit for TEST ⁵
I
–0.25
DT
0
mA
13 Storage temperature range
Tstg
–65
155
°C
1 _{Beyond absolute maximum ratings device might be damaged.}
2 _{The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute}
maximum ratings apply when the device is powered from an external source.
3 _{All digital I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA.}
4 _{Those pins are internally clamped to VSSPLL and VDDPLL.}
5 _{This pin is clamped low to VSSPLL, but not clamped high. This pin must be tied low in applications.}
A.1.6 ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 stress test qualification for automotive grade
integrated circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM) and the Charge Device Model.
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
Freescale Semiconductor
MC9S12XDP512 Data Sheet, Rev. 2.21
1241