MC9S12XD256MAL Datasheet, PDF (903/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Port
E
Table 23-1. Pin Functions and Priorities (Sheet 2 of 7)
Pin Name
PE[7]
Pin Function
and Priority
XCLKS¹
ECLKX2
GPIO
MODB¹
PE[6]
TAGHI
PE[5]
GPIO
MODA¹
RE
TAGLO
GPIO
PE[4]
PE[3]
PE[2]
PE[1]
PE[0]
ECLK
GPIO
EROMCTL¹
LSTRB
LDS
GPIO
R/W
WE
GPIO
IRQ
GPIO
XIRQ
GPIO
I/O
Description
I External clock selection input during RESET
I Free-running clock output at Core Clock rate (ECLK x 2)
I/O General-purpose I/O
I MODB input during RESET
I
Instruction tagging low pin
Configurable for reduced input threshold
I/O General-purpose I/O
I MODA input during RESET
O Read enable signal
I
Instruction tagging low pin
Configurable for reduced input threshold
I/O General-purpose I/O
O
Free-running clock output at the Bus Clock rate or
programmable divided in normal modes
I/O General-purpose I/O
I EROMON bit control input during RESET
O Low strobe bar output
O Lower data strobe
I/O General-purpose I/O
O Read/write output for external bus
O Write enable signal
I/O General-purpose I/O
I Maskable level- or falling edge-sensitive interrupt input
I/O General-purpose I/O
I Non-maskable level-sensitive interrupt input
I/O General-purpose I/O
Pin Function
after Reset
Mode
dependent³