MC9S12XD256MAL Datasheet, PDF (829/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2.7 Port C Data Direction Register (DDRC)
R
W
Reset
7
DDRC7
0
6
DDRC6
5
DDRC5
4
DDRC4
3
DDRC3
2
DDRC2
0
0
0
0
0
Figure 22-9. Port C Data Direction Register (DDRC)
1
DDRC1
0
0
DDRC0
0
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data are read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Table 22-10. DDRC Field Descriptions
Field
Description
7–0
DDRC[7:0]
Data Direction Port C — This register controls the data direction for port C. When Port C is operating as a general
purpose I/O port, DDRC determines whether each pin is an input or output. A logic level “1” causes the
associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PORTC after changing the DDRC register.
22.3.2.8 Port D Data Direction Register (DDRD)
R
W
Reset
7
DDRD7
0
6
DDRD6
5
DDRD5
4
DDRD4
3
DDRD3
2
DDRD2
0
0
0
0
0
Figure 22-10. Port D Data Direction Register (DDRD)
1
DDRD1
0
0
DDRD0
0
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data are read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Table 22-11. DDRD Field Descriptions
Field
Description
7–0
DDRD[7:0]
Data Direction Port D — This register controls the data direction for port D. When Port D is operating as a general
purpose I/O port, DDRD determines whether each pin is an input or output. A logic level “1” causes the
associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PORTD after changing the DDRD register.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
831