MC9S12XD256MAL Datasheet, PDF (926/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
23.0.5.13 ECLK Control Register (ECLKCTL)
7
6
5
4
3
R
0
0
0
NECLK NCLKX2
W
Reset¹ Mode
Dependent
1
0
0
0
SS
0
1
0
0
0
ES
1
1
0
0
0
ST
0
1
0
0
0
EX
0
1
0
0
0
NS
1
1
0
0
0
NX
0
1
0
0
0
2
1
0
0
EDIV1
EDIV0
0
0
0
Mode
0
0
0
Special
Single-Chip
0
0
0
Emulation
Single-Chip
0
0
0
Special
Test
0
0
0
Emulation
Expanded
0
0
0
Normal
Single-Chip
0
0
0
Normal
Expanded
= Unimplemented or Reserved
Figure 23-15. ECLK Control Register (ECLKCTL)
1. Reset values in emulation modes are identical to those of the target mode.
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
The ECLKCTL register is used to control the availability of the free-running clocks and the free-running
clock divider.
Table 23-16. ECLKCTL Field Descriptions
Field
7
NECLK
Description
No ECLK — This bit controls the availability of a free-running clock on the ECLK pin. Clock output is always
active in emulation modes and if enabled in all other operating modes.
0 ECLK enabled
1 ECLK disabled
MC9S12XDP512 Data Sheet, Rev. 2.21
928
Freescale Semiconductor