MC9S12XD256MAL Datasheet, PDF (585/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

BDM Clock
(Target MCU)
Chapter 15 Background Debug Module (S12XBDMV2)
Host
Transmit 1
Host
Transmit 0
Perceived
Start of Bit Time
Target Senses Bit
10 Cycles
Synchronization
Uncertainty
Figure 15-8. BDM Host-to-Target Serial Bit Timing
Earliest
Start of
Next Bit
The receive cases are more complicated. Figure 15-9 shows the host receiving a logic 1 from the target
system. Since the host is asynchronous to the target, there is up to one clock-cycle delay from the
host-generated falling edge on BKGD to the perceived start of the bit time in the target. The host holds the
BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must
release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the
perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it
started the bit time.
BDM Clock
(Target MCU)
Host
Drive to
BKGD Pin
Target System
Speedup
Pulse
Perceived
Start of Bit Time
BKGD Pin
High-Impedance
R-C Rise
High-Impedance
High-Impedance
10 Cycles
10 Cycles
Host Samples
BKGD Pin
Figure 15-9. BDM Target-to-Host Serial Bit Timing (Logic 1)
Earliest
Start of
Next Bit
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
585