MC9S12XD256MAL Datasheet, PDF (835/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
Table 22-16. ECLKCTL Field Descriptions (continued)
Field
Description
6
NCLKX2
1–0
EDIV[1:0]
No ECLKX2 — This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a fixed
rate of twice the internal bus clock. Clock output is always active in emulation modes and if enabled in all other
operating modes.
0 ECLKX2 is enabled
1 ECLKX2 is disabled
Free-Running ECLK Divider — These bits determine the rate of the free-running clock on the ECLK pin. The
usage of the bits is shown in Table 22-17. Divider is always disabled in emulation modes and active as
programmed in all other operating modes.
Table 22-17. Free-Running ECLK Clock Rate
EDIV[1:0]
00
01
10
11
Rate of Free-Running ECLK
ECLK = Bus clock rate
ECLK = Bus clock rate divided by 2
ECLK = Bus clock rate divided by 3
ECLK = Bus clock rate divided by 4
22.3.2.14 IRQ Control Register (IRQCR)
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
IRQE
IRQEN
W
Reset
0
1
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 22-16. IRQ Control Register (IRQCR)
Read: See individual bit descriptions below.
Write: See individual bit descriptions below.
Table 22-18. IRQCR Field Descriptions
Field
7
IRQE
6
IRQEN
Description
IRQ Select Edge Sensitive Only
Special modes: Read or write anytime.
Normal and emulation modes: Read anytime, write once.
0 IRQ configured for low level recognition.
1 IRQ configured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime
IRQE = 1 and will be cleared only upon a reset or the servicing of the IRQ interrupt.
External IRQ Enable
Read or write anytime.
0 External IRQ pin is disconnected from interrupt logic.
1 External IRQ pin is connected to interrupt logic.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
837