MC9S12XD256MAL Datasheet, PDF (69/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 1 Device Overview MC9S12XD-Family
The CAN modules may be configured to have their clock sources derived either from the bus clock or
directly from the oscillator clock. This allows the user to select its clock based on the required jitter
performance. Consult MSCAN block description for more details on the operation and configuration of
the CAN blocks.
In order to ensure the presence of the clock the MCU includes an on-chip clock monitor connected to the
output of the oscillator. The clock monitor can be configured to invoke the PLL self-clocking mode or to
generate a system reset if it is allowed to time out as a result of no oscillator clock being present.
In addition to the clock monitor, the MCU also provides a clock quality checker which performs a more
accurate check of the clock. The clock quality checker counts a predetermined number of clock edges
within a defined time window to insure that the clock is running. The checker can be invoked following
specific events such as on wake-up or clock monitor failure.
1.4 Chip Configuration Summary
CAUTION
Emulation single chip mode, Normal expanded mode, Emulation expanded
mode and ROMCTL/EROMCTL functionality is only available on parts
with external bus interface in 144 LQFP package. see Appendix E
Derivative Differences.
The MCU can operate in six different modes. The different modes, the state of ROMCTL and EROMCTL
signal on rising edge of RESET, and the security state of the MCU affects the following device
characteristics:
• External bus interface configuration
• Flash in memory map, or not
• Debug features enabled or disabled
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA signals
during reset (see Table 1-9). The MODC, MODB, and MODA bits in the MODE register show the current
operating mode and provide limited mode switching during operation. The states of the MODC, MODB,
and MODA signals are latched into these bits on the rising edge of RESET.
In normal expanded mode and in emulation modes the ROMON bit and the EROMON bit in the
MMCCTL1 register defines if the on chip flash memory is the memory map, or not. (See Table 1-9.) For
a detailed description of the ROMON and EROMON bits refer to the S12X_MMC section.
The state of the ROMCTL signal is latched into the ROMON bit in the MMCCTL1 register on the rising
edge of RESET. The state of the EROMCTL signal is latched into the EROMON bit in the MISC register
on the rising edge of RESET.
The MCU can operate in two different modes. The operating mode out of reset is determined by the state
of the MODC signal during reset. The MODC bit in the MODE register shows the current operating mode
and provide limited mode switching during operation. The state of the MODC signal is latched into this
bit on the rising edge of RESET.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
69