MC9S12XD256MAL Datasheet, PDF (505/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 11 Serial Communication Interface (S12SCIV5)
In Figure 11-22 the verification samples RT3 and RT5 determine that the first low detected was noise and
not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise flag
is not set because the noise occurred before the start bit was found.
Start Bit
LSB
RXD
Samples 1 1 1 0
1
110
0
0
0000
RT Clock
RT Clock Count
Reset RT Clock
Figure 11-22. Start Bit Search Example 1
In Figure 11-23, verification sample at RT3 is high. The RT3 sample sets the noise flag. Although the
perceived bit time is misaligned, the data samples RT8, RT9, and RT10 are within the bit time and data
recovery is successful.
Perceived Start Bit
Actual Start Bit
LSB
RXD
Samples 1 1 1 1 1 0
1
0
0000
RT Clock
RT Clock Count
Reset RT Clock
Figure 11-23. Start Bit Search Example 2
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
505