MC9S12XD256MAL Datasheet, PDF (130/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description
Register
Name
0x000D
ATDDIEN1
Bit 7
R
IEN7
W
6
IEN6
5
IEN5
4
IEN4
3
IEN3
2
IEN2
1
IEN1
0x000E
PORTAD0
R PTAD15
W
PTAD14
PTAD13
PTAD12
PTAD11
PTAD10
PTAD9
0x000F
PORTAD1
R PTAD7
W
PTAD6
PTAD5
PTAD4
PTAD3
PTAD2
PTAD1
R BIT 9 MSB
BIT 7 MSB
0x0010–0x002F W
ATDDRxH–
ATDDRxL R
BIT 1
u
W
BIT 8
BIT 6
BIT 0
u
BIT 7
BIT 5
0
0
BIT 6
BIT 4
0
0
BIT 5
BIT 3
0
0
BIT 4
BIT 2
0
0
BIT 3
BIT 1
0
0
= Unimplemented or Reserved
u = Unaffected
Figure 4-2. ATD Register Summary (continued)
Bit 0
IEN0
PTAD8
PTAD0
BIT 2
BIT 0
0
0
4.3.2.1 ATD Control Register 0 (ATDCTL0)
Writes to this register will abort current conversion sequence but will not start a new sequence.
7
R
0
W
Reset
0
Read: Anytime
Write: Anytime
6
5
4
3
2
0
0
0
WRAP3
WRAP2
0
0
0
1
1
= Unimplemented or Reserved
Figure 4-3. ATD Control Register 0 (ATDCTL0)
Table 4-2. ATDCTL0 Field Descriptions
1
WRAP1
1
0
WRAP0
1
Field
Description
3:0
Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing
WRAP[3:0] multi-channel conversions. The coding is summarized in Table 4-3.
MC9S12XDP512 Data Sheet, Rev. 2.21
130
Freescale Semiconductor